chiller carrier
Electronics
parti 2
.9.1 TEC Controller
The TEC controller circuit is a step-down switching converter that uses 24V as input and outputs a variable voltage up to 2.2A at 2.3V at an efficiency of 78%. The output is adjusted so that the thermistor on the APD package maintains a constant temperature of -15C. The circuit has been designed to minimize the output ripple so that it does not add significant additional noise to APD output. A photograph of the circuit as built and tested is shown in Figure14.18.
Fig. 14.18: Photograph of power circuit for TEC regulation
.9.2 Signal Extraction
The front end electronics has the responsibility of amplifying and integrating the signals from the APD arrays, determining the amplitude of the signals and their arrival time and presenting that information to the data acquisition system (DAQ). The front-end electronics will operate in continuous digitization mode and does not require any external trigger or NUMI timing gate. Data will be time stamped and compared to a NUMI timing signal in the DAQ system to determine if the event was in or out of spill.
Data from the ADC is sent to an FPGA where multiple correlated sampling is used to remove low frequency noise. This type of Digital Signal Processing (DSP) also reduces the noise level and increases the time resolution.
The interface to the DAQ can be configured to send up to 16Mbits/s, or up to 6.2kHz/channel. The typical rate expected is due to cosmic ray muons, and will produce an average hit rate of 120Hz/cell, 2% of the link capacity. As many as 64 FEBs feed a single data concentrator, with a 1Gbit uplink speed. This limits each link to an upper limit of 15.6Mbits/s, effectively matching the maximum FEB uplink speed, with only 2% of the capacity used on average.
To prevent unnecessarily loading the DAQ system upstream links and buffer farm it is important to keep the data rate from noise to an acceptable level. The noise level of the front end electronics and the imposed threshold determines the noise data rates. Figure 14.19 shows the simulated noise rate per 32 channel APD box as a function of threshold for 2.3 effective photoelectrons of noise per channel, 10 bytes of information per hit above threshold and 106 time slices/second. The noise includes the APD excess noise in amplifying the bulk current. In order to keep the noise data rate on the order of the rate from cosmic ray muons (with a modest
Data from the ADC is sent to an FPGA where multiple correlated sampling is used to remove low frequency noise. This type of Digital Signal Processing (DSP) also reduces the noise level and increases the time resolution.
The interface to the DAQ can be configured to send up to 16Mbits/s, or up to 6.2kHz/channel. The typical rate expected is due to cosmic ray muons, and will produce an average hit rate of 120Hz/cell, 2% of the link capacity. As many as 64 FEBs feed a single data concentrator, with a 1Gbit uplink speed. This limits each link to an upper limit of 15.6Mbits/s, effectively matching the maximum FEB uplink speed, with only 2% of the capacity used on average.
To prevent unnecessarily loading the DAQ system upstream links and buffer farm it is important to keep the data rate from noise to an acceptable level. The noise level of the front end electronics and the imposed threshold determines the noise data rates. Figure 14.19 shows the simulated noise rate per 32 channel APD box as a function of threshold for 2.3 effective photoelectrons of noise per channel, 10 bytes of information per hit above threshold and 106 time slices/second. The noise includes the APD excess noise in amplifying the bulk current. In order to keep the noise data rate on the order of the rate from cosmic ray muons (with a modest
overburden) it is necessary to impose a 12-15 photoelectron threshold. In the near detector this threshold can be increased to reduce the noise component even further since the signals are expected to be approximately 4 times larger due to the short length of the modules.
The NOvA power distribution system (PDS) supplies power to five different electronic components used in the readout: front end boards (FEBs), avalanche photodiodes (APDs), thermoelectric coolers (TECs), data concentrator modules (DCMs), and timing distribution units (TDUs). The power distribution system consists of: 1) the power supplies and their racks, 2) the power distribution boxes that fan out the power to the FEBs, APDs, TECs, and DCMs, and 3) the power cables and their cable trays. Two similar systems are needed: one for the near detector and one for the far detector. The large number of channels and the extent of the detectors demand that the systems must be remotely controllable. The systems must also be robust and safe. The voltage, current, and power requirements for the five components are given in Table 14.3.
Fig. 14.19: The simulated data rate at the NOvA far detector, in bits per second, as a function of the readout threshold. Noise is due to the amplifier noise, assumed to be 1.5ENC, bulk dark current of 1.5e/micros, amplified by the APD with its characteristic excess noise factor of 2.5. The data rate due to cosmic ray muons, with a modest overburden, is also indicated as well as the networking technologies necessary to accommodate various rates.
.9.3 Operating modes
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The front end electronics must operate in several different modes that can be selected through the DAQ interface. These are:
• Run Mode – The Front end electronics will continuously acquire and transmit data to the DAQ system.
• Calibration mode – Data is accumulated for calibration and for determining thresholds and pedestals, noise measurements, etc.
• Test Mode – The Front end electronics must be able to simulate data and send specific test patterns to the DAQ system to check for proper operation.
• Programming mode – The front end electronics must be able to download and upload data that define its operating parameters. The front end electronics must have on-board firmware that can be reprogrammed in place via the DAQ system.
The front end electronics must operate in several different modes that can be selected through the DAQ interface. These are:
• Run Mode – The Front end electronics will continuously acquire and transmit data to the DAQ system.
• Calibration mode – Data is accumulated for calibration and for determining thresholds and pedestals, noise measurements, etc.
• Test Mode – The Front end electronics must be able to simulate data and send specific test patterns to the DAQ system to check for proper operation.
• Programming mode – The front end electronics must be able to download and upload data that define its operating parameters. The front end electronics must have on-board firmware that can be reprogrammed in place via the DAQ system.
9.4 Digital Signal Processing
The FPGA on the FEB uses a digital signal processing algorithm to extract the time and amplitude of signals from the APD. Any signal above a pre-programmed threshold will be time-stamped and sent to the DAQ for processing. The threshold is settable at the channel level to allow different thresholds to be set depending on the particular characteristics of a given channel.
The DSP algorithm uses many samples to extract the time and amplitude of the signals. This is possible since there is very little activity in any given channel. Typically 20 samples are used in the current algorithm. The extra samples help to average out the current noise component of the signal to obtain better timing resolution than would normally be expected with 500ns digitization. It also has the effect of reducing the effective noise component by approximately 20%, giving a 20% increase in the signal to noise ratio.
A sample trace is shown for an ideal signal and one with additional noise in Figure 14.20. A matched filtering technique is used to transform the signal to a symmetric output pulse shown in Figure 14.21. The discrete points in the filter output can then be interpolated to obtain the peak with approximately four times greater resolution. The FEB will use this interpolated filter output shown in Figure 14.22 to create a timestamp with a 62.5ns bin size, eight times smaller than the sampling time of 500ns.
The FPGA on the FEB uses a digital signal processing algorithm to extract the time and amplitude of signals from the APD. Any signal above a pre-programmed threshold will be time-stamped and sent to the DAQ for processing. The threshold is settable at the channel level to allow different thresholds to be set depending on the particular characteristics of a given channel.
The DSP algorithm uses many samples to extract the time and amplitude of the signals. This is possible since there is very little activity in any given channel. Typically 20 samples are used in the current algorithm. The extra samples help to average out the current noise component of the signal to obtain better timing resolution than would normally be expected with 500ns digitization. It also has the effect of reducing the effective noise component by approximately 20%, giving a 20% increase in the signal to noise ratio.
A sample trace is shown for an ideal signal and one with additional noise in Figure 14.20. A matched filtering technique is used to transform the signal to a symmetric output pulse shown in Figure 14.21. The discrete points in the filter output can then be interpolated to obtain the peak with approximately four times greater resolution. The FEB will use this interpolated filter output shown in Figure 14.22 to create a timestamp with a 62.5ns bin size, eight times smaller than the sampling time of 500ns.
10 Power Distribution
The NOvA power distribution system (PDS) supplies power to five different electronic components used in the readout: front end boards (FEBs), avalanche photodiodes (APDs), thermoelectric coolers (TECs), data concentrator modules (DCMs), and timing distribution units (TDUs). The power distribution system consists of: 1) the power supplies and their racks, 2) the power distribution boxes that fan out the power to the FEBs, APDs, TECs, and DCMs, and 3) the power cables and their cable trays. Two similar systems are needed: one for the near detector and one for the far detector. The large number of channels and the extent of the detectors demand that the systems must be remotely controllable. The systems must also be robust and safe. The voltage, current, and power requirements for the five components are given in Table 14.3.
Power Distribution Box
|
|||||
Module
|
Voltage (V)
|
Current (A)
|
Channels
|
Total Current
|
Power (W)
|
FEB
|
3.3
|
1.0
|
60-64
|
60-64 A
|
211
|
TEC
|
24.
|
0.15
|
60-64
|
9-10 A
|
240
|
APD
|
350-450
|
0.00004
|
60-64
|
2.4.-2.6
mA
|
2
|
DCM
|
24.
|
1.25
|
1
|
1.25 A
|
30
|
TDU
|
24.
|
1.0
|
1/24
|
1.0 A
|
24
|
Table 14.3 Power
requirements for the front-end electronics.
The layout of the power distribution system is shown schematically in Figure 14.23. All power to the front-end electronics is distributed by power distribution boxes (PDBs) which are situated on the detector. An isometric view of a custom power distribution box is shown in Figure 14.24. A single 6-conductor, 18AWG cable from each PDB output carries the 450V The layout of the power distribution system is shown schematically in Figure 14.23. All power to the front-end electronics is distributed by power distribution boxes (PDBs) which are situated on the detector. An isometric view of a custom power distribution box is shown in Figure 14.24. A single 6-conductor, 18AWG cable from each PDB output carries the 450V
needed by the APDs, the 24V needed by the TE coolers, as well as the 3.3V needed by the FEBs, as well as their return currents. All the electronic components and the power supplies float: ground reference is at the PDBs. A maximum of 64 FEBs and 1 DCM are served by each PDB.
Fig. 14.23: Schematic of the NOvA power distribution system. Each power distribution box feeds 3.3V, 24V, and 450V via a single cable to a maximum of 64 front-end boards, and 24V via a single cable to the nearby data concentrator module. The APD voltage to the power distribution boxes is provided by CAEN A1520P cards situated in a CAEN SY1527LC mainframe. The FEB, TE cooler, and DCM voltages are provided by Wiener PL508 power supplies.
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