6/06/2014

chiller carrier Electronics parti 1

chiller carrier 
Electronics
parti 1

carrier electronics
.6      APD Cooling
.6.1      Thermoelectric Coolers
A single-stage TE cooler will cool each APD array.  The APD module has been tested with a TEC from TE Technology, TE-31-1.0-1.3, with specifications given in Table 14.2.  This has a maximum cooling capacity of 8.4W, and size to match the APD array.  Measurements with a prototype APD module have shown a TE cooler electrical power requirement of 2.1W, and heat removal of less than 2W to maintain an APD temperature of -15ºC.  The TE cooler and power supplies have additional headroom of 3.2W and 5W respectively.  The system should quickly and easily reach operating temperature.  The TE cooler must not apply significant mechanical stress to the APD array, so we deploy a deformable, thermally conducting crush pad between the TE cooler and the APD array.  The thermal power generated in the APD array itself is ~2 mecroW, so the thermal load will come from other components through the mechanical and electrical interconnects.  The TE cooler will generate approximately 3W of heat for each 32 channel APD array.
Given the industry standard reliability of a TEC of 200,000 hours MTBF, or 22.3 years, we expect a 4%/year failure rate of the TE coolers.  The APD module is designed to allow replacement of the TEC without complete removal from the detector module.

Part Number     Qmax (W)      Imax  (A)     Vmax  (V)    dTMax (C)    Width (mm)    Length (mm)    Height (mm)
TE-31-1.0-1.3    8.4    3.6    3.8    69    14.8    14.8    3.6

Table 14.2  Specification for TEC tested with the APD module
.
.6.2      Water Cooling System
  Liquid cooling is a reliable and effective means of removing the heat from the TE coolers.  The high heat capacity of water facilitates the removal of the required heat without requiring large temperature differences.  We will use a chilled water system that provides approximately 2mL/s of 15C water to remove the heat from each TE cooler.  The water will be supplied by cooling loops covering a pair of blocks.  Each loop will service 744 TE coolers.  Commercially produced compact process water chillers with a capacity of 7kW and capabilities similar to Neslab  HX-300 will be installed at the head end of each loop on the highest catwalk level.  The chillers will reject heat directly to air. Each chiller is capable of maintaining its water output temperature within +/- 0.1 deg C of a setpoint. A block diagram of a cooling loop is shown in 
Figures 14.9 and 14.10.  Water is distributed to the cooling elements via a supply and return manifold system.  The system is arranged with reverse return flow to help naturally balance the flow through each element.  A monitoring station in each loop housing control and monitoring equipment provides an interface to the Detector Control System.  There are 17  complete cooling loops for the entire detector.  The 17 chillers and monitoring stations are located approximately every 14 feet along the length of the detector.
Distribution manifolds supply water to the 24 service(hose) manifold sections, 12 on the side and 12 on the top of the detector.  The supply and return service  manifolds in each location will be identical.  The general features of a manifold are shown in Figure 14.11.  Each service manifold provides 32 hose connections with valved quick disconnect connectors at their ends.  The service manifolds are installed as two sections that correspond to a pair of 31 plane blocks.  This matches the readout electronics commissioning as well. 
Fig. 14.9.: Schematic of single water cooling loop.




Fig. 14.11:  Service Manifold Section.
Supervisory control and monitoring of the cooling system will be integrated as part of the Detector Controls system.  It will log historical data, manage alarms, and be the primary human interface to the cooling system. While monitoring supply and return temperatures, pressures, flow, and level in each water cooling loop, it will be able to remotely turn the chiller units on and off, and adjust the chiller temperature setpoints to optimize cooling performance. A block diagram of
one of the loop remote control systems is shown in Figure 14.12.  Screens presenting realtime cooling system data will be accessible to technicians in the detector hall via a wireless network to facilitate maintenance and troubleshooting
.  In addition, portable readout units will be available to directly monitor the sensor data and control signals for comissioning and troubleshooting. These simple electronic readouts will plug in to the sensor junction boxes at each chiller station and will not depend on the ethernet or Detector Control computer systems.
Each chiller includes a local control panel allowing manual override of remote control if necessary.
Fig. 14.12:  Pump control and loop instrumentation

One important function of the control system, leak detection, will be accomplished by coolant level monitoring in the chiller reservoirs. The control system will alert operators and can automatically shut down systems to minimize damage and conserve coolant. In the worst case, a major leak resulting in rapid loss of the entire volume of a cooling loop would involve less than 62 gallons of water.
To minimize the peak electrical and building air cooling loads at startup, the control system will automatically sequence the application of power to groups of cooling loops, allowing one group to stabilize before starting another. This would keep both the peak and stabilized net heat rejected to air at about 93kW, assuming 3.35w per APD module, steady state.
Each chiller requires about 3kW electric power. With all chillers running, this would total 51kW. This energy, converted to heat, makes up a large portion of the heat-to-air load mentioned above. Since this chiller load is virtually all from induction motors, the power factor will be poor, and may require corrective measures..
.7      Low Noise ASIC Amplifier
A custom ASIC has been developed for NOvA to maximize the sensitivity of the detector to small signals from extremely long fibers in the far detector.  The schematic is shown in Figure 14.13 with a micrograph of the device that was produced shown in Figure 14.4.   Signals from individual APD pixels are processed through individual amplifier and pulse-shaping stages before being multiplexed to an ADC in sets of 8 channels.  The ADC is external to the ASIC and is a commercial component.  A schematic of the layout is shown in Figure 14.15. 


Fig. 14.13:  NOvA custom ASIC schematic

Fig 14.14:  Micrograph of prototype readout ASIC

Fig. 14.15: Schematic of the Front End ASIC and external ADC for NOvA

The computed noise level for the chip that we have designed specifically to operate with an APD with a gain of 100 and cooled to -15C is 150 electrons.  The noise measured on a prototype is 100 electrons for the optimal input transistor.  Our calculations assume that this will increase to 150electrons when packaged and mounted on the FEB.  With an APD gain of 100, this 150 electrons RMS noise reduces to 1.5 photoelectrons equivalent.  At -15C we also expect up to 16 thermally generated electrons every 1s.  The convolution of the amplifier noise with the APD noise results in a mean of 4 photoelectrons of noise.  This is to be compared to an average photoelectron yield at the far end of an extrusion module of 30, spread over a very short time interval.  This design will have good separation of signal and noise.

.8      Special Electronics Version for the Near Detector

The NOvA Near Detector will receive a high rate of neutrino interactions, and will also receive a large number of particles from the tunnel walls (see Chapter 6, Section 6.6.3).  Detector simulations indicate that the high occupancy during a spill requires better double pulse separation than is possible using the standard electronics from the far detector.  For simplicity and cost effectiveness we intend to use as many of the same components as possible in each detector.  The detector will therefore use the same APD and TEC.  The front-end of the low noise ASIC amplifier is also identical to that of the far detector.  The ASIC will be modified from the prototype to have additional output amplifiers and multiplexing logic to operate with only 2:1 multiplexing instead of 8:1 as is used in the far detector, increasing the sampling frequency by a factor of 4.  The additional amplifiers will be switched off for use at the far detector.  This design will use four times as many ADCs as the far detector due to the decreased multiplexing.  This will .

increase the sampling rate by a factor of four.  The prototype for this ASIC is currently being designed.  There are not expected to be any technical problems in implementing a selectable multiplexing scheme since it has been done before to implement a selectable 16:1 or 4:1 multiplexing on the MASDA ASIC we have used for detector development.  In this case it is expected that the same ASIC can be used for the far detector as well with some additional logic to disable the additional amplifiers and increase the number of channels each amplifier is multiplexing.  The additional sampling and higher light yields in the smaller detector will aid in detecting and reconstructing the overlapping events in the detector.

.9      Front End Boards

The Front-end Electronics board (FEB) is connected to the APD carrier board through a short ribbon cable.  In addition to the front end ASIC and ADC, the front-end board contains a connector for interfacing to the DAQ system, TE cooler controller circuitry, DACs and ADCs for control and monitoring, and an FPGA for doing digital signal processing, I/O functions, and general board monitoring.  The front end boards require low voltage to power the electronics and the TE cooler controller.  The front end electronics boards will each require 3 W of clean power at 3 V.  The TE coolers will require 2-5 W to be provided at 24 V.  Low voltage power is discussed in Section 14.10.  A sketch of the front-end board and the APD carrier board is shown in Figure 14.16.  Layout of the critical components is shown in Figure 14.17.
Fig. 14.16:  Schematic of the APD module and the front-end electronics board showing the major components.  

Fig. 14.17:  Layout of the FEB.  Major components are the carrier board connector location at the left, which brings the APD signals to the NOvA ASIC, which performs integration, shaping, and multiplexing. The chip immediately to the right is the ADC to digitize the signals, and FPGA for control, signal processing, and communication.

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